He is working on the Automatic Device Driver Synthesis project. He is currently looking at ways to build a compiler which would compile HDLs such as Verilog and VHDL into an intermediate form which could then be used to synthesize the driver.
Graduate Engineer at ARM.
CPU Design & Verification Engineer at ARM.
Worked for 4 years at ARM on Various ARM processors(Cortex M3, Cortex R4, Cortex M1), Coresight components such as ETM, DAP(debug access port), ATB(AMBA trace bus) designs etc.
Gained strong experience in the following:
ARM architecture and processor designs(Verilog designs).
Design of programmer's model of devices, Bus functional models of processor components such as Data processing Unit, LSU, PFU etc, constrained random stimulus generation, drivers, monitors, scoreboards in languages such as Verilog, System Verilog, Specman-e and C++.
ARM architecture and device specific validation suites using ARM assembly.
Performed research on evaluation of System Verilog to make a strategic decision on the language to be used by ARM future designs.
Bachelor of Engineering in Information Technology(CSE)
Master of Engineering in computing and Microelectronics.
| Email: | balachandra.mirla@nicta.com.au |
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